Intel Celeron Processor

Introduction

The Intel Celeron Processor is a new processor offering based on the Intel P6 microarchitecture, the same microarchitecture on which the Pentium II processor is based. It provides a base level of functionality to meet the core needs and affordability requirements common to many new home and business users. The first member of this new product line is the Celeron processor at 266 MHz with a system bus of 66 MHz.

While evaluating the performance of a microprocessor, it is important to get a complete picture of how it executes various tasks. The increasing use of 3D and multimedia content in software today is placing new demands on the microprocessor. Typical productivity applications such as word processing, presentation applications or personal finance programs require the processor to have good integer performance. Applications such as video playback, 3D games & PC imaging stress the multimedia and floating- point capabilities of the processor and the system. For the best all round computation, a system should deliver high performance in all three of these areas: integer, multimedia & floating point. Not every processor is equally capable of the same performance for each type of application such as multimedia, 3D geometric calculations, floating point & integer applications and software applications etc. Specifically, benchmarks designed for evaluating these vectors should be used to look at the complete performance of the processor or the system.

The Intel Celeron processor provides good performance applications running on operating system such as Windows 95, Windows NT & UNIX.

The Intel Celeron Processor

The Intel Celeron processor meets the core needs & affordability requirements common to many new users while providing the performance required for applications running on an operating system such as Windows 95. The processor core has 7.5 million transistors and is based on Intel’s advanced 0.25 micron CMOS process technology. The Celeron processor is backed by Intel’s 25 years of engineering experience manufacturing high quality, reliable, compatible microprocessors. It is provided in a single edge processor package(S.E.P.P.) enabling ease of design as well as cost efficiency. This packaging technology features a core processor based on the P6 architecture on a single sided substrate without BSRAM component. There is no thermal plate or cover. Due to the lower power dissipation of the 0.25 micron process technology the heat sink size has been reduced.

Product Feature Highlights

The Celeron is fully compatible with an entire library of PC software based on operating systems such as MS-DOS, Windows 3.1, Windows for workgroups 3.11, Windows 95, OS/2, UNIXWARE, SCO UNIX, Windows NT, OPENSTEP and Sun Solaris.

Architectural Features

Dynamic Execution Technology

The Intel Celeron processor has Dynamic execution technology which incorporates the concepts of out of order and speculative execution. The Celeron processor’s implementation of these concepts removes the constraint of linear instruction sequencing between the traditional fetch & execute phases of instruction execution. Up to three instructions can be decoded per clock cycle. These decoded instructions are put into a data flow graph which can hold upto 40 instructions. Instructions are executed from this graph when their operands are available. Up to four instructions can be executed per clock cycle.

Super-Pipelining

The pipeline of the P6 processor family consists of approximately 12 stages versus 5 for the Pentium processor and 6 for the Pentium processor with MMX technology. This enables the Celeron processor to achieve about a 50% higher frequency than the Pentium processor on the same manufacturing technology. The sophisticated dynamic, two level adaptive-training, branch prediction mechanism of the P6 micro-architecture is key to maintaining the efficiency of the Intel Celeron processor’s super-pipelined micro-architecture.

High Performance Intel MMX Technology

Intel’s MMX media enhancement technology is a major enhancement to the Intel architecture which makes PCs richer multimedia and communications platforms. This technology introduces 57 instructions oriented to highly parallel operations with multimedia and communications data types. These instructions use a technique known as SIMD(Single instruction multiple data) to deliver better performance for multimedia & communications computation. Intel processors that provide MMX technology support are fully compatible with previous generations of the Intel architecture and the installed base of software. To further improve performance, the Celeron processor like the P-II processor, can execute two Intel MMX instructions simultaneously.

Write Combining

The write combining technology of the P6 processor family can be utilized to get very high graphics I/O performance. This feature combines multiple writes to a region of memory declared as WC type into a single burst write operation. This is well suited for the bus which is optimized for burst transfers. The combining also leads to burst writes of cache line sizes. These writes are further combined by the chipset leading to high throughput for graphics I/O. This will further enhance multimedia performance and enable more realistic full motion video and realistic, fast graphics performance.

Caches

The Celeron processor has 32 KB of non-blocking L1 cache which is divided into a 16 KB instruction and 16 KB data cache. Each of these cache run at the processor frequency and provide fast access to heavily used data.

Floating point pipeline which supports the 32 bit & 64 bit IEEE 754 formats as well as the 80 bit format. The FPU is object code compatible with Pentium and 486 processor FPUs.

Testing And Performance Monitoring Features

Built in self test which provides single stuck at fault coverage of the microcode and large PLAs as well as testing of the instruction cache, data cache, Translation look aside buffers(TLBs) and ROMs. IEEE 1149.1 standard test access port and boundary scan architecture mechanism which allows testing of the Celeron processor through a standard interface. Internal performance counters for performance monitoring and event counting.